`include "cpu_def.vh"

module hi_lo(
  input        clk,
  input [63:0] hi_lo_wdata,
  input [ 1:0] hi_lo_wen,
  input [ 1:0] hi_lo_raddr,

  output [31:0] hi_lo_rdata
);

  reg [31:0] hi_lo [1:0];
  wire [31:0] hi_lo_d [1:0];

  assign hi_lo_d[`LO] = hi_lo_wdata[31: 0];
  assign hi_lo_d[`HI] = hi_lo_wdata[63: 32];

  always@(posedge clk)begin
    if (hi_lo_wen[`LO]) begin
      hi_lo[`LO] <= hi_lo_d[`LO];
    end

    if (hi_lo_wen[`HI]) begin
      hi_lo[`HI] <= hi_lo_d[`HI];
    end
  end

  assign hi_lo_rdata = {32{hi_lo_raddr[0]}} & hi_lo[`LO] |
                       {32{hi_lo_raddr[1]}} & hi_lo[`HI];

endmodule
